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1024k x 8 mobl static ram cy62158cv25/30/33 mobl? cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05019 rev. *b revised january 18, 2002 features high speed ? 55 ns and 70 ns availability voltage range: ? cy62158cv25: 2.2v ? 2.7v ? cy62158cv30: 2.7v ? 3.3v ? cy62158cv33: 3.0v ? 3.6v ultra low active power ? typical active current: 1 ma @ f = 1 mhz ? typical active current: 7 ma @ f = f max (70 ns speed) low standby power easy memory expansion with ce 1 , ce 2 and oe features automatic power-down when deselected cmos for optimum speed/power functional description the cy62158cv25/30/33 are high-performance cmos static rams organized as 1024k words by 8 bits. this device fea- tures advanced circuit design to provide ultra-low active cur- rent. this is ideal for providing more battery life ? (mobl ? ) in portable applications such as cellular telephones. the de- vice also has an automatic power-down feature that signifi- cantly reduces power consumption by 80% when addresses are not toggling. the device can be put into standby mode reducing power consumption by more than 99% when dese- lected (ce 1 high or ce 2 low). writing to the device is accomplished by taking chip enable (ce 1 low and ce 2 high) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip en- able (ce 1 low and ce 2 high) and output enable (oe ) low while forcing write enable (we ) high. under these condi- tions, the contents of the memory location specified by the address pins will appear on the i/o pins. the eight input/output pins (i/o 0 through i/o 7 ) are placed in a high-impedance state when the device is deselected (ce 1 low and ce 2 high), the outputs are disabled (oe high), or during a write operation (ce 1 low and ce 2 high and we low). the cy62158cv25/30/33 are available in a 48-ball fbga package. logic block diagram mobl, mobl2 and more battery life are trademarks of cypress semiconductor corporation a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 1024k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 14 a 13 a 16 a 18 a 15 a 17 a 9 a 19 ce 1 ce 2 a 10 a 11 a 12
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 2 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature . ................................ ? 65 c to +150 c ambient temperature with power applied. ..............................................55 c to +125 c supply voltage to ground potential ... ? 0.5v to v ccmax + 0.5v dc voltage applied to outputs in high z state [3] .................................... ? 0.5v to v cc + 0.5v dc input voltage [3] ................................. ? 0.5v to v cc + 0.5v output current into outputs (low)..............................20 ma static discharge voltage ............................................>2001v (per mil-std-883, method 3015) latch-up current .....................................................>200 ma notes: 1. nc pins are not connected to the die. 2. c2 (dnu) can be left as nc or v ss to ensure proper application. 3. v il(min.) = ? 2.0v for pulse durations less than 20 ns. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. pin configurations we v cc a 11 a 10 a 6 a 0 a 3 ce 1 dnu nc i/o 0 a 4 a 5 i/o 1 nc i/o 2 i/o 3 nc a 9 a 8 oe v ss a 7 nc nc ce 2 a 17 a 2 a 1 nc v cc i/o 4 nc i/o 5 i/o 6 nc i/o 7 nc a 15 a 14 a 13 a 12 nc a 18 a 19 3 2 6 5 4 1 d e b a c f g h a 16 nc fbga top view [1, 2] v ss operating range product range ambient temperature v cc cy62158cv25 industrial ? 40 c to +85 c 2.2v to 2.7v cy62158cv30 2.7v to 3.3v cy62158cv33 3.0v to 3.6v product portfolio product v cc range speed power dissipation (industrial) operating (i cc ) standby (i sb2 ) f = 1 mhz f = f max min. typ. [4] max. typ. [4] max. typ. [4] max. typ. [4] max. cy62158cv25 2.2v 2.5v 2.7v 55 ns 1.5 ma 3 ma 12 ma 25 ma 6 a 25 a 70 ns 1.5 ma 3 ma 7 ma 15 ma cy62158cv30 2.7v 3.0v 3.3v 55 ns 1.5 ma 3 ma 12 ma 25 ma 8 a 25 a 70 ns 1.5 ma 3 ma 7 ma 15 ma cy62158cv33 3.0v 3.3v 3.6v 55 ns 1.5 ma 3 ma 12 ma 25 ma 10 a 30 a 70 ns 1.5 ma 3 ma 7 ma 15 ma
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 3 of 12 electrical characteristics over the operating range cy62158cv25-55 cy62158cv25-70 parameter description test conditions min. typ. [4] max. min. typ. [4] max. unit v oh output high voltage i oh = ? 0.1 ma v cc = 2.2v 2.0 2.0 v v ol output low voltage i ol = 0.1 ma v cc = 2.2v 0.4 0.4 v v ih input high voltage 1.8 v cc + 0.3v 1.8 v cc + 0.3v v v il input low voltage ? 0.3 0.6 ? 0.3 0.6 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 2.7v i out = 0 ma cmos levels 12 25 7 15 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe ,we ) 6 25 6 25 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 2.7v cy62158cv30-55 cy62158cv30-70 parameter description test conditions min. typ. [4] max. min. typ. [4] max. unit v oh output high voltage i oh = ? 1.0 ma v cc = 2.7v 2.4 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 2.7v 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage ? 0.3 0.8 ? 0.3 0.8 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.3v i out = 0 ma cmos levels 12 25 7 15 ma f = 1 mhz 1.5 3 1.5 3 i sb1 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we ) 8 25 8 25 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0,v cc = 3.3v
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 4 of 12 capacitance [5] electrical characteristics over the operating range (continued) cy62158cv33-55 cy62158cv33-70 parameter description test conditions min. typ. [4] max. min. typ. [4] max. unit v oh output high voltage i oh = ? 1.0 ma v cc = 3.0v 2.4 2.4 v v ol output low voltage i ol = 2.1 ma v cc = 3.0v 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage ? 0.3 0.8 ? 0.3 0.8 v i ix input leakage current gnd < v i < v cc ? 1 +1 ? 1 +1 a i oz output leakage current gnd < v o < v cc , output disabled ? 1 +1 ? 1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = 3.6v i out = 0 ma cmos levels 12 25 7 15 ma f = 1 mhz 1 2 1 2 i sb1 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = f max (address and data only), f=0 (oe , we ) 10 30 10 30 a i sb2 automatic ce power-down cur- rent ? cmos inputs ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc = 3.6v parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ.) 6 pf c out output capacitance 8 pf thermal resistance description test conditions symbol bga unit thermal resistance [5] (junction to ambient) still air, soldered on a 4.25 x 1.125 inch, 4-layer print- ed circuit board ja 55 c/w thermal resistance [5] (junction to case) jc 16 c/w note: 5. tested initially and after any design or process changes that may affect these parameters.
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 5 of 12 ac test loads and waveforms parameters 2.5v 3.0v 3.3v unit r1 16.6 1.105 1.216 k ? r2 15.4 1.550 1.374 k ? r th 8 0.645 0.645 k ? s v th 1.20 1.75 1.75 volts data retention characteristics (over the operating range) parameter description conditions min. typ. [4] max. unit v dr v cc for data retention 1.5 v ccmax v i ccdr data retention current v cc = 1.5v ce 1 > v cc ? 0.2v or ce 2 < 0.2v v in > v cc ? 0.2v or v in < 0.2v 4 20 a t cdr [5] chip deselect to data retention time 0 ns t r [6] operation recovery time t rc ns data retention waveform note: 6. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 s or stable at v cc(min.) > 100 s. v cc typ v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: th venin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns v cc(min) v cc(min) t cdr v dr > 1.5 v data retention mode t r ce 1 v cc ce 2 or
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 6 of 12 switching characteristics over the operating range [7] parameter description 55 ns 70 ns min. max. min. max. unit read cycle t rc read cycle time 55 70 ns t aa address to data valid 55 70 ns t oha data hold from address change 10 10 ns t ace ce 1 low and ce 2 high to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [8] 5 5 ns t hzoe oe high to high z [8, 9] 20 25 ns t lzce ce 1 low and ce 2 high to low z [8] 10 10 ns t hzce ce 1 high or ce 2 low to high z [8, 9] 20 25 ns t pu ce 1 low and ce 2 high to power-up 0 0 ns t pd ce 1 high or ce 2 low to power-down 55 70 ns write cycle [10] t wc write cycle time 55 70 ns t sce ce 1 low and ce 2 high to write end 45 60 ns t aw address set-up to write end 45 60 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 45 50 ns t sd data set-up to write end 25 30 ns t hd data hold from write end 0 0 ns t hzwe we low to high z [8, 9] 20 25 ns t lzwe we high to low z [8] 5 5 ns notes: 7. test conditions assume signal transition time of 5 ns or less, timing reference levels of v cc(typ.) /2, input pulse levels of 0 to v cc(typ.) , and output loading of the specified i ol /i oh and 30-pf load capacitance. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzce , and t hzwe transitions are measured when the outputs enter a high impedance state. 10. the internal write time of the memory is defined by the overlap of we , ce = v il , and ce 2 = v ih . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge o f the signal that terminates the write.
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 7 of 12 switching waveforms notes: 11. device is continuously selected. oe , ce 1 = v il , ce 2 =v ih . 12. we is high for read cycle. 13. address valid prior to or coincident with ce 1 transition low and ce 2 transition high. address data out previous data valid data valid t rc t aa t oha read cycle no. 1 (address transition controlled) [11, 12] 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce 1 i cc i sb impedance address ce 2 data out v cc supply current read cycle no. 2 (oe controlled) [12, 13]
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 8 of 12 notes: 14. data i/o is high impedance if oe = v ih . 15. during this period, the i/os are in output state and input signals should not be applied. 16. if ce 1 goes high or ce 2 goes low simultaneously with we high, the output remains in high-impedance state. switching waveforms t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce 1 address ce 2 we data i/o oe note 15 write cycle no. 1(we controlled) [10, 14, 16] t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce 1 address ce 2 we data i/o write cycle no. 2(ce 1 or ce 2 controlled) [10, 14, 16] oe
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 9 of 12 switching waveforms data in valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce 1 address ce 2 we data i/o note 15 write cycle no. 3 (we controlled, oe low) [16]
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 10 of 12 typical dc and ac characteristics (typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c.) truth table ce 1 ce 2 we oe inputs/outputs mode power h x x x high z deselect/power-down standby (i sb ) x l x x high z deselect/power-down standby (i sb ) l h h l data out (i/o 0 -i/o 7 ) read active (i cc ) l h h h high z output disabled active (icc) l h l x data in (i/o 0 -i/o 7 ) write active (icc) 12.0 10.0 6.0 4.0 0 8.0 i sb ( a) 12.0 10.0 6.0 4.0 2.0 2.2 0.0 8.0 i cc (ma) supply voltage (v) supply voltage (v) mobl2 mobl2 mobl2 2.2 2.0 (f = f max , 55 ns) (f = 1 mhz) (f = f max , 70 ns) 14.0 2.5 2.7 2.5 2.7 12.0 10.0 6.0 4.0 2.0 2.7 3.3 0.0 8.0 i cc (ma) supply voltage (v) mobl2 (f = f max , 55 ns) (f = 1 mhz) (f = f max , 70 ns) 14.0 3.0 12.0 10.0 6.0 4.0 2.0 3.0 3.6 0.0 8.0 i cc (ma) supply voltage (v) (f = f max , 55 ns) (f = 1 mhz) (f = f max , 70 ns) 14.0 3.3 mobl2 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) supply voltage (v) 3.6 2.0 3.3 12.0 10.0 6.0 4.0 3.0 0 8.0 i sb ( a) standby current vs. supply voltage supply voltage (v) mobl2 2.0 2.7 3.3 50 30 20 10 3.0 3.6 supply voltage (v) 0 40 t aa (ns) 60 3.3 50 30 20 10 2.2 supply voltage (v) 0 40 t aa (ns) 60 2.5 2.7 50 30 20 10 supply voltage (v) access time vs. supply voltage 0 40 t aa (ns) 60 3.0 2.7 3.3 mobl2 operating current vs. supply voltage mobl2 mobl2 mobl2
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 11 of 12 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. ordering information speed (ns) ordering code package name package type operating range 70 cy62158cv25ll-70bai ba48f 48-ball fine pitch bga industrial cy62158cv30ll-70bai cy62158cv33ll-70bai 55 CY62158CV25LL-55BAI cy62158cv30ll-55bai cy62158cv33ll-55bai package diagrams 48-ball (6 mm x 10 mm x 1.2 mm) fbga ba48f 51-85128-*b
cy62158cv25/30/33 mobl ? document #: 38-05019 rev. *b page 12 of 12 document title: cy62158cv25/30/33 mobl ? , 1024k x 8 mobl static ram document number: 38-05019 rev. ecn no. issue date orig. of change description of change ** 106361 05/22/01 mgn new data sheet - advance information *a 107773 07/16/01 mgn add 55 ns bin to advance information *b 111945 01/31/02 gav advance to final

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